Fan Hu

About Me

Hi! I am Fan Hu, a first-year Ph.D. candidate in Electronic Science and Technology at Shanghai Jiao Tong University, advised by Prof. Xinfei Guo, and I conduct my research in the Intelligent Circuits, Architectures, and Systems (iCAS) Lab. Before beginning my doctoral study, I received my B.S. in Electrical and Computer Engineering from Shanghai Jiao Tong University.

My research interests lie in AI for Electronic Design Automation (EDA), with a particular focus on applying AI to timing prediction and optimization in the early stages of the EDA flow. I am also interested in reliability-aware chip design, especially understanding and addressing aging effects in advanced semiconductor technologies.

AI for EDATiming Optimization for Advanced ChipsReliable Circuits

Education

Shanghai Jiao Tong University seal

2024—Present

Ph.D. in Electronic Science and Technology

Shanghai Jiao Tong University · Shanghai, China

Advisor: Prof. Xinfei Guo

Shanghai Jiao Tong University seal

2020—2024

B.S. in Electrical and Computer Engineering

Shanghai Jiao Tong University · Shanghai, China

News

  • My first-author paper, RESIST: Residual Reinforcement Learning for Lifespan Clock Tree Reliability Optimization, has been accepted by ICCD'26!

  • I received the 2026 IEEE CASS Student Travel Grant!

  • My first-author paper, Beyond Iterative Search: Intelligent Generative GATv2 Framework for Analog Sizing, has been accepted by AICAS'26!

  • Our co-authored paper, Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits, has been published in ACM Computing Surveys!

Show earlier news

  • Our co-first-authored paper, Shift-Left Techniques in Electronic Design Automation: A Survey, has been published in ACM Computing Surveys!

  • Our co-authored paper, ChiPlanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems, has been accepted by DAC'26!

  • Our team received multiple awards in the EDA Elite Competition for AI-based, cross-process behavioral modeling of analog integrated circuits!

  • I received the 2024 Annual Excellent Teaching Assistant Award from Global College, Shanghai Jiao Tong University!

  • Our iCAS team secured a Winning Award at the AICAS 2025 Grand Challenge by designing a two-stage operational amplifier using LLMs! Congratulations!

  • Our team won second place in the EDA Elite Competition for Chiplet Partitioner with Timing-Driven Placement!

Main Research Topics

AI for EDA

Generative, reinforcement-learning, and agentic approaches for analog and digital circuit design automation.

Timing prediction & optimization

Learning-based timing prediction and timing-driven optimization for advanced chips, including 3D ICs, with an emphasis on early physical design decisions.

Reliability-aware design

Design methodologies that account for aging, stress, and long-term reliability in integrated circuits.

Publications

Google Scholar

† Equal contribution (co-first authors)* Corresponding author

First-Author Work

ICCD 2026Overview of the RESIST lifespan timing optimization framework

Conference paper · First author

RESIST: Residual Reinforcement Learning for Lifespan Clock Tree Reliability Optimization

F. Hu, X. Wu, H. Wang, J. Shaik, S. Singhal, and X. Guo*

IEEE International Conference on Computer Design (ICCD), 2026.

AICAS 2026Overview of the generative GATv2 analog sizing framework

Conference paper · First author

Beyond Iterative Search: Intelligent Generative GATv2 Framework for Analog Sizing

F. Hu, J. Shaik, and X. Guo*

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2026.

ACM CSURShift-left techniques across the electronic design automation flow

Journal paper · Co-first author

Shift Left Techniques in Electronic Design Automation: A Survey

X. Wu†, Z. Li†, F. Hu†, T. Lin, X. Zhao, R. Wang, and X. Guo*

ACM Computing Surveys (CSUR), 2026.

DOI · 10.1145/3819588

COLLABORATIVE WORK

Conference paper

ChiPlanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems

Z. Li†, K. Tian†, F. Hu, Z. Li, X. Wu, H. Zhang, S. Chen, J. Zhai*, X. Guo*, and K. Zhao

ACM/IEEE Design Automation Conference (DAC), 2026.

Conference paper

Aging Analysis of CMOS Synaptic Circuits with Simplified Leaky Integrate-and-Fire Neurons

S. J. Babu, S. Menezes Picard, F. Hu, X. Wu, S. Singhal, and X. Guo*

IEEE International Conference on Mobile Services and Cloud Computing (McSoC), 2026.

Conference paper

PRISM: Beam-Search Technology Mapping via Learned Physical Timing

L. Zhu, X. Wu, F. Hu, L. Li, Y. Hu, Q. He, and X. Guo*

23rd International SoC Design Conference (ISOCC), 2026.

Journal paperDOI · 10.1145/3829075

Extending Silicon Lifetime: A Review of Design Techniques for Reliable Integrated Circuits

J. Shaik, F. Hu, L. Zhu, S. Singha, and X. Guo*

ACM Computing Surveys (CSUR), 2026.

Book / Book Chapter

AI-Powered Vehicles: Computing Power and Chips for Intelligent Driving

X. Guo, R. Wang, F. Hu, and X. Wu

China Mechanical Industry Press, 2026. ISBN: 9787111799894. (In Chinese).

Honors & Awards

IEEE CASS Student Travel Grant2026
Outstanding Teaching Assistant Award, Global College, SJTU2025
Winning Award, AICAS Grand Challenge: LLM-Based Analog Circuit Design Competition2025
Third Prize, EDA Elite Competition2025
Second Prize, EDA Elite Competition2024
Show earlier honors & awards
Honorable Mention, MCM for College Students2022, 2023
Outstanding Undergraduate B-level Scholarship, SJTU2022
Outstanding Undergraduate Progress Scholarship, SJTU2022
University-Level Merit Student, SJTU2022
Silver Medal, University Physics Competition2021

Services

IEEE Student Membership.
Core Member, ACM-W SJTU Student Organization.
Reviewer for DAC, ICCAD, ICCD, ISCAS, and ISEDA conferences.

Teaching

Teaching Assistant, Global College, Shanghai Jiao Tong University.

System-on-Chip Design2025
Modern Digital VLSI Design2025
Electromagnetics2024
Introduction to Circuits2023
Introduction to Signals and Systems2023